1. Field of the Invention
This invention relates to a display apparatus for a double speed video signal wherein an input video signal is converted into another double speed image signal and a standard television signal is displayed together with a child picture on a screen of a television receiver, for example, for the high definition television system.
2. Description of the Related Art
When it is tried to display a television signal of a standard system such as the NTSC system, PAL system or SECAM system on a high definition television receiver, preferably a video signal is processed, according to the compatibility of the deflection system, at a double speed to display the image in a double field frequency or a double line frequency.
For example, the PAL/SECAM television system adopted in Europe employs a 2:1 interlace system of 625 lines/50 Hz, and accordingly, when a video signal of high brightness is displayed, a large screen flicker is usually seen. In order to eliminate this large screen flicker, it has been proposed to use double speed field display means which performs double speed processing to double the field frequency of a video signal to make a parent picture and repetitively display odd-/even-numbered field signals of 312.5 H and 312.5 H twice in different fields like odd-/odd-/even-/even-numbered fields of 312 H, 312.5 H, 313 H and 312.5 H.
Similarly, for the NTSC system, a superimposed line double speed system has been proposed wherein signals of odd-numbered and even-numbered fields of 262.5 H and 262.5 H are processed at a line double speed to produce field signals of 525 H and 525 H and upper and lower instances of horizontal lines which display the same signal are superimposed with each other so as to perform scanning equivalent to that of a normal interlace system. Such technique is disclosed, for example, in EP 0,482,894, A2.
A similar technique is disclosed in EP 0,551,168, Al wherein a television signal of a standard television system is displayed together with a child picture on a screen of a television receiver of, for example, the high definition television system.
However, where it is tried to simultaneously display a child picture in a superimposed condition on a parent picture processed by double speed signal processing in such a manner as described above, the following problems are encountered.
A. Where the parent picture is a field double speed picture:
1. Also a child picture to be inserted into the parent picture must necessarily be processed by field double speed processing, and to this end, it has been proposed to determine a sequence of read-out areas of a four field sequence memory using a normal speed vertical synchronizing signal as a clock signal for the four field sequence memory for displaying a child picture at a field double speed, latch the child picture signal in response to a vertical synchronizing pulse signal of a double speed to that of the deflection system to delay the child picture by a time corresponding to one field of the double speed and use the thus delayed child picture signal as a control signal for a read-out memory area for the child picture. However, it sometimes occurs that a control signal for a write memory area exhibits overlapping by a time equal to the delay time, and there is a problem in that the memory area which undergoes writing and the memory area which undergoes reading out coincide with each other to cause passing of a memory address for a child picture with the probability of 1/8. PA0 2. One of simple methods of processing a parent picture by double speed processing by four times for odd-numbered, odd-numbered, even-numbered and even-numbered fields is a field display mode wherein only one of the odd-numbered and even-numbered fields of a child picture video signal written in a memory is repetitively read out and displayed by four times. The method, however, has a problem in that motion of the child picture is skipped by one field and the vertical resolution of the child picture is reduced to one half or less than that of ordinary frames. PA0 1. Since the superimposed line double speed conversion system basically involves non-interlace conversion timings, there is a problem in that discrimination between odd- and even-numbered fields is impossible after conversion into picture of a double speed and, when a child picture video signal is converted, after such double speed conversion, into a signal of a double speed and then displayed, the interlace of child picture images is reversed with the probability of 1/2. PA0 2. It may be possible to shift, in a zoom mode wherein a 4:3 video signal is displayed fully on a 16:9 video screen by over-scanning of the upper and lower portions of the 4:3 video signal by a vertical deflection system, a video signal of a child picture prior to double speed conversion so as to be superimposed on a video signal of a parent picture to effect line double speed processing. In this case, however, such complicated scanning is involved that, when a zoomed display picture of the parent picture is scrolled, it is shifted, for example, in the opposite direction so that the position of the child picture may not be varied. PA0 3. When a parent picture is processed by line double speed processing and the signal obtained by the line double speed processing is superimposed to obtain an image of the interlace system, the upper and lower lines of same signal portions of the video signal after double speed conversion are superimposed in the opposite directions to each other between odd- and even-numbered fields by a deflection system. In this case, there is a problem in that, if a child picture processed by field double speed processing is displayed in a superimposed relationship on the double speed image signal, when the odd-numbered field is normal, the superimposition of the upper and lower lines of the child picture in the even-numbered fields is reversed.
B. When a parent picture is converted into a line double speed video signal and a display picture of the interlace system is produced by superimposition: